loading...
Test-per-Clock Detection, Localization and Identification of Interconnect Faults
Southampton, United Kingdom May 21-May 21
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2006.45Eleventh IEEE European Test Symposium ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka, "Test-per-Clock Detection, Localization and Identification of Interconnect Faults," European Test Symposium, IEEE, pp. 233-238, Eleventh IEEE European Test Symposium (ETS'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/ETS.2006.45,
author = {Michal Kopec and Tomasz Garbolino and Krzysztof Gucwa and Andrzej Hlawiczka},
title = {Test-per-Clock Detection, Localization and Identification of Interconnect Faults},
journal ={European Test Symposium, IEEE},
volume = {0},
year = {2006},
issn = {1530-1877},
pages = {233-238},
doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2006.45},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - European Test Symposium, IEEE
TI - Test-per-Clock Detection, Localization and Identification of Interconnect Faults
SN - 1530-1877
SP233
EP238
A1 - Michal Kopec,
A1 - Tomasz Garbolino,
A1 - Krzysztof Gucwa,
A1 - Andrzej Hlawiczka,
PY - 2006
KW - null
VL - 0
JA - European Test Symposium, IEEE
ER -
 
Michal Kopec, Silesian University of Technology, Poland
Tomasz Garbolino, Silesian University of Technology, Poland
Krzysztof Gucwa, Silesian University of Technology, Poland
Andrzej Hlawiczka, Silesian University of Technology, Poland
The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable.
Citation:
Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka, "Test-per-Clock Detection, Localization and Identification of Interconnect Faults," ets, pp.233-238, Eleventh IEEE European Test Symposium (ETS'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.