Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism

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http://doi.ieeecomputersociety.org/10.1109/ETS.2006.48

Eleventh IEEE European Test Symposium ...

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	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes, "Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism," European Test Symposium, IEEE, pp. 213-218, Eleventh IEEE European Test Symposium (ETS'06), 2006.

	BibTex	x
	@article{ 10.1109/ETS.2006.48, author = {Alexandre M. Amory and Kees Goossens and Erik Jan Marinissen and Marcelo Lubaszewski and Fernando Moraes}, title = {Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism}, journal ={European Test Symposium, IEEE}, volume = {0}, year = {2006}, issn = {1530-1877}, pages = {213-218}, doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2006.48}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - European Test Symposium, IEEE TI - Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism SN - 1530-1877 SP213 EP218 A1 - Alexandre M. Amory, A1 - Kees Goossens, A1 - Erik Jan Marinissen, A1 - Marcelo Lubaszewski, A1 - Fernando Moraes, PY - 2006 KW - null VL - 0 JA - European Test Symposium, IEEE ER -

Alexandre M. Amory, Federal University of RGS - UFRG, Brazil

Kees Goossens, Philips Research Laboratories, The Netherlands

Erik Jan Marinissen, Philips Research Laboratories, The Netherlands

Marcelo Lubaszewski, Federal University of RGS - UFRGS, Brazil

Fernando Moraes, Catholic University - PUCRS, Brazil

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the ?thereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM.

Citation:

Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes, "Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism," ets, pp.213-218, Eleventh IEEE European Test Symposium (ETS'06), 2006

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