loading...
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
Freiburg, Germany May 20-May 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.112th IEEE European Test Symposium (ET ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
V. Kerzerho, P. Cauvet, S. Bernard, F. Azais, M. Comte, M. Renovell, ""Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC," European Test Symposium, IEEE, pp. 211-216, 12th IEEE European Test Symposium (ETS'07), 2007.
 
 
BibTex
x
 
@article{ 10.1109/ETS.2007.1,
author = {V. Kerzerho and P. Cauvet and S. Bernard and F. Azais and M. Comte and M. Renovell},
title = {"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC},
journal ={European Test Symposium, IEEE},
volume = {0},
year = {2007},
issn = {1530-1877},
pages = {211-216},
doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2007.1},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - European Test Symposium, IEEE
TI - "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
SN - 1530-1877
SP211
EP216
A1 - V. Kerzerho,
A1 - P. Cauvet,
A1 - S. Bernard,
A1 - F. Azais,
A1 - M. Comte,
A1 - M. Renovell,
PY - 2007
KW - null
VL - 0
JA - European Test Symposium, IEEE
ER -
 
V. Kerzerho, LIRMM, University of Montpellier/CNRS, France; Philips France Semiconducteurs
P. Cauvet, Philips France Semiconducteurs
S. Bernard, LIRMM, University of Montpellier/CNRS, France
F. Azais, LIRMM, University of Montpellier/CNRS, France
M. Comte, LIRMM, University of Montpellier/CNRS, France
M. Renovell, LIRMM, University of Montpellier/CNRS, France
In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "Analogue Network of Converters" (ANC) requires an extremely simple additional circuitry and interconnect.
Citation:
V. Kerzerho, P. Cauvet, S. Bernard, F. Azais, M. Comte, M. Renovell, ""Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC," ets, pp.211-216, 12th IEEE European Test Symposium (ETS'07), 2007
Usage of this product signifies your acceptance of the Terms of Use.