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Electronics Design-for-Test: Past, Present and Future
Freiburg, Germany May 20-May 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.2112th IEEE European Test Symposium (ET ...
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Ben Bennetts, "Electronics Design-for-Test: Past, Present and Future," European Test Symposium, IEEE, pp. 4, 12th IEEE European Test Symposium (ETS'07), 2007.
 
 
BibTex
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@article{ 10.1109/ETS.2007.21,
author = {Ben Bennetts},
title = {Electronics Design-for-Test: Past, Present and Future},
journal ={European Test Symposium, IEEE},
volume = {0},
year = {2007},
issn = {1530-1877},
pages = {4},
doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2007.21},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - European Test Symposium, IEEE
TI - Electronics Design-for-Test: Past, Present and Future
SN - 1530-1877
SP
EP
A1 - Ben Bennetts,
PY - 2007
KW - null
VL - 0
JA - European Test Symposium, IEEE
ER -
 
Ben Bennetts, ex-DFT Consultant, UK
Do you know how many ENIAC vacuum tubes were replaced every day during its heyday? What did it teach us about Test, or Design-For-Test? Did Eldred really invent the stuck-at fault model in 1959? Is 99.999% fault cover all it?s cracked up to be or are we fooling ourselves? Are we better off with 115% or even 80%? Where did Design-For-Test come from? Where is it now? Where?s it heading? Is it true that boundary scan is the panacea of test? What are all these new Joint Test Action Groups -- Internal, System and compact? Are they boondoggles, or are they serious?
Citation:
Ben Bennetts, "Electronics Design-for-Test: Past, Present and Future," ets, pp.4, 12th IEEE European Test Symposium (ETS'07), 2007
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