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PPM Reduction on Embedded Memories in System on Chip
Freiburg, Germany May 20-May 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.3312th IEEE European Test Symposium (ET ...
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Said Hamdioui, Zaid Al-Ars, Javier Jimenez, Jose Calero, "PPM Reduction on Embedded Memories in System on Chip," European Test Symposium, IEEE, pp. 85-90, 12th IEEE European Test Symposium (ETS'07), 2007.
 
 
BibTex
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@article{ 10.1109/ETS.2007.33,
author = {Said Hamdioui and Zaid Al-Ars and Javier Jimenez and Jose Calero},
title = {PPM Reduction on Embedded Memories in System on Chip},
journal ={European Test Symposium, IEEE},
volume = {0},
year = {2007},
issn = {1530-1877},
pages = {85-90},
doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2007.33},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - European Test Symposium, IEEE
TI - PPM Reduction on Embedded Memories in System on Chip
SN - 1530-1877
SP85
EP90
A1 - Said Hamdioui,
A1 - Zaid Al-Ars,
A1 - Javier Jimenez,
A1 - Jose Calero,
PY - 2007
KW - memory testing
KW - static faults
KW - dynamic faults
KW - PPM reduction.
VL - 0
JA - European Test Symposium, IEEE
ER -
 
Said Hamdioui, Delft University of Technology, The Netherlands
Zaid Al-Ars, Delft University of Technology, The Netherlands
Javier Jimenez, Design of Systems on Silicon (DS2), Spain
Jose Calero, Design of Systems on Silicon (DS2), Spain
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests are industrially evaluated together with the traditional tests at "Design of Systems on Silicon (DS2)" in Spain in order to (a) validate the used fault models and (b) investigate the added value of the new tests and their impact on the PPM level. The preliminary silicon results are presented and analyzed. They validate some of the new dynamic fault models and show the importance of considering dynamic faults for high outgoing product quality.
Index Terms:
memory testing, static faults, dynamic faults, PPM reduction.
Citation:
Said Hamdioui, Zaid Al-Ars, Javier Jimenez, Jose Calero, "PPM Reduction on Embedded Memories in System on Chip," ets, pp.85-90, 12th IEEE European Test Symposium (ETS'07), 2007
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