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A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification
San Jose, California, USA November 12-November 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FMCAD.2006.2Formal Methods in Computer Aided Desi ...
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Husam Abu-Haimed, Nusym Technology, Inc, USA
David L. Dill, Stanford University, USA
Sergey Berezin, Synopsys, Inc, USA
We introduce a heuristic for automatically checking the validity of first-order formulas of the form \forall \alpha ^m \exists \beta ^n. \Psi \left( {\alpha ^m ,\beta ^n } \right) that are encountered in inductive proofs of hardware correctness. The heuristic introduced in this paper is used to automatically check the validity of k-step induction formulas needed to verify hardware designs. The heuristic works on word-level designs that can have data and address buses of arbitrary widths. Our refinement heuristic relies on the idea of predicate instantiation introduced in [2]. The heuristic proves quantified formulas by the use of a validity checker, CVC [21], and a first-order theorem prover, Otter [16]. Our heuristic can be used as a stand-alone technique to verify word-level designs or as a component in an interactive theorem prover. We show the effectiveness of this heuristic for hardware verification by verifying a number of hardware designs completely automatically. The large size of the quantified formulas encountered in these examples shows the effectiveness of our heuristic as a component of a theorem prover.
Citation:
Husam Abu-Haimed, David L. Dill, Sergey Berezin, "A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification," fmcad, pp.145-152, Formal Methods in Computer Aided Design (FMCAD'06), 2006
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