Acceleration of an FPGA router

Napa Valley, CA April 16-April 18

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http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624617

5th IEEE Symposium on FPGA-Based Cust ...

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	ASCII Text	x
	P.K. Chan, M.D.F. Schlag, "Acceleration of an FPGA router," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 175, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997.

	BibTex	x
	@article{ 10.1109/FPGA.1997.624617, author = {P.K. Chan and M.D.F. Schlag}, title = {Acceleration of an FPGA router}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1997}, issn = {1082-3409}, pages = {175}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624617}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Acceleration of an FPGA router SN - 1082-3409 SP EP A1 - P.K. Chan, A1 - M.D.F. Schlag, PY - 1997 KW - field programmable gate arrays; FPGA router acceleration; routing; placement; automatic chip design; programmable logic device configuration; reconfigurable computing elements; processor clusters; hardware acceleration; coarse-grain parallelism; fine-grain parallelism VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

P.K. Chan, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

M.D.F. Schlag, Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

The authors describe their experience and progress in accelerating an FPGA router. Placement and routing is undoubtedly the most time-consuming process in automatic chip design or configuring programmable logic devices as reconfigurable computing elements. Their goal is to accelerate routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration. Coarse-grain parallelism is exploited by having several processors route separate groups of nets in parallel. A hardware accelerator is presented which exploits the fine-grain parallelism in routing individual nets.

Index Terms:

field programmable gate arrays; FPGA router acceleration; routing; placement; automatic chip design; programmable logic device configuration; reconfigurable computing elements; processor clusters; hardware acceleration; coarse-grain parallelism; fine-grain parallelism

Citation:

P.K. Chan, M.D.F. Schlag, "Acceleration of an FPGA router," fccm, pp.175, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997

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