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Fault simulation on reconfigurable hardware
Napa Valley, CA April 16-April 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.6246185th IEEE Symposium on FPGA-Based Cust ...
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M. Abramovici, Lucent Technols., Bell Labs., Murray Hill, NJ, USA
P. Menon, Lucent Technols., Bell Labs., Murray Hill, NJ, USA
The authors introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. The performance estimate shows that the approach is at least on order of magnitude faster than serial fault emulation used in prior work.
Index Terms:
reconfigurable architectures; reconfigurable hardware; fault simulation; critical path tracing algorithm; performance estimate; combinational circuits
Citation:
M. Abramovici, P. Menon, "Fault simulation on reconfigurable hardware," fccm, pp.182, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997
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