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Scan testing of asynchronous sequential circuits
The State University of New York at Buffalo March 16-March 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516057Fifth Great Lakes Symposium on VLSI ( ...
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O.A. Petlin, S.B. Furber, "Scan testing of asynchronous sequential circuits," Great Lakes Symposium on VLSI, pp. 224, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516057,
author = {O.A. Petlin and S.B. Furber},
title = {Scan testing of asynchronous sequential circuits},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {224},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516057},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Scan testing of asynchronous sequential circuits
SN - 1066-1395
SP
EP
A1 - O.A. Petlin,
A1 - S.B. Furber,
PY - 1995
KW - logic testing; sequential circuits; boundary scan testing; logic design; integrated logic circuits; integrated circuit testing; VLSI; asynchronous circuits; asynchronous sequential logic; delays; asynchronous sequential circuits; micropipeline design style; scan testing; combinational block; single stuck-at faults; delay faults; state holding elements; standard test generation techniques
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
O.A. Petlin, Dept. of Comput. Sci., Oxford Univ., UK
S.B. Furber, Dept. of Comput. Sci., Oxford Univ., UK
A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.
Index Terms:
logic testing; sequential circuits; boundary scan testing; logic design; integrated logic circuits; integrated circuit testing; VLSI; asynchronous circuits; asynchronous sequential logic; delays; asynchronous sequential circuits; micropipeline design style; scan testing; combinational block; single stuck-at faults; delay faults; state holding elements; standard test generation techniques
Citation:
O.A. Petlin, S.B. Furber, "Scan testing of asynchronous sequential circuits," glsvlsi, pp.224, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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