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An all Digital BiCMOS Phase Lock Loop for VLSI Processors
Ann Arbor, Michigan March 04-March 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757442Ninth Great Lakes Symposium on VLSI
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Lim Chu Aun, Intel Microelectronics
S.M. Rezaul Hasan, Universiti Sains Malaysia
A BiCMOS all digital phase lock loop is described. This design is suitable for applications such as clock recovegi and frequency synthesis in VLSI processors where thermal stability is an important factor. The main block qf the design consists of a digitally controlled oscillator with wide frequent, range & high thermal stabiliv compared to CMOS design. Improved BiCMOS adder/subtracter was also implemented to reduce worst-case propagation de&time. A small test chip was fabricated using MOSIS Orbit 2,~nn low-cost analog CMOS process technology that provides lateral NPN bipolar device option.
Citation:
Lim Chu Aun, S.M. Rezaul Hasan, "An all Digital BiCMOS Phase Lock Loop for VLSI Processors," glsvlsi, pp.318, Ninth Great Lakes Symposium on VLSI, 1999
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