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Advances in Quantum Computing Fault Tolerance and Testing
Dallas, Texas, USA November 14-November 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HASE.2007.5310th IEEE High Assurance Systems Engi ...
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David Y. Feinstein, V.S.S. Nair, Mitchell A. Thornton, "Advances in Quantum Computing Fault Tolerance and Testing," High-Assurance Systems Engineering, IEEE International Symposium on, pp. 369-370, 10th IEEE High Assurance Systems Engineering Symposium (HASE'07), 2007.
 
 
BibTex
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@article{ 10.1109/HASE.2007.53,
author = {David Y. Feinstein and V.S.S. Nair and Mitchell A. Thornton},
title = {Advances in Quantum Computing Fault Tolerance and Testing},
journal ={High-Assurance Systems Engineering, IEEE International Symposium on},
volume = {0},
year = {2007},
issn = {1530-2059},
pages = {369-370},
doi = {http://doi.ieeecomputersociety.org/10.1109/HASE.2007.53},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - High-Assurance Systems Engineering, IEEE International Symposium on
TI - Advances in Quantum Computing Fault Tolerance and Testing
SN - 1530-2059
SP369
EP370
A1 - David Y. Feinstein,
A1 - V.S.S. Nair,
A1 - Mitchell A. Thornton,
PY - 2007
KW - null
VL - 0
JA - High-Assurance Systems Engineering, IEEE International Symposium on
ER -
 
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustrate the inherent need for fault tolerance in QC due to the decoherence problem. Further, we examine several ideas regarding random testing and examine the viability of built-insystem-test (BIST) in future QC circuits.
Citation:
David Y. Feinstein, V.S.S. Nair, Mitchell A. Thornton, "Advances in Quantum Computing Fault Tolerance and Testing," hase, pp.369-370, 10th IEEE High Assurance Systems Engineering Symposium (HASE'07), 2007
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