Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the chip?s array of processors can be tailored to their program, creating an application-specific multiprocessor. While much Hardware/Software Codesign research has been conducted on optimizing heterogeneous processing arrays, shortcomings exist in design scalability, simulation, verification, rapid prototyping, and the requirement of specialized skill sets.

To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point connections. By individually optimizing each processor for its specific program the performance of the array is increased, while the common basic interface between processors eases optimization, implementation, debugging, and verification.