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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
August 26-August 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HOTI.2008.112008 16th IEEE Symposium on High Perf ...
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We present a new monolithic silicon photonics technology suited for integration with standard bulk CMOS processes, which reduces costs and improves opto-electrical coupling compared to previous approaches. Our technology supports dense wavelength-division multiplexing with dozens of wavelengths per waveguide. Simulation and experimental results reveal an order of magnitude better energy-efficiency than electrical links in the same technology generation. Exploiting key features of our photonics technology, we have developed a processor-memory network architecture for future manycore systems based on an opto-electrical global crossbar. We illustrate the advantages of the proposed network architecture using analytical models and simulations with synthetic traffic patterns. For a power-constrained system with 256 cores connected to 16 DRAM modules using an opto-electrical crossbar, aggregate network throughput can be improved by ~8-10x compared to an optimized purely electrical network.
Citation:
Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Vladimir Stojanovic, Krste Asanovic, "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics," hoti, pp.21-30, 2008 16th IEEE Symposium on High Performance Interconnects, 2008
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