loading...
Power-Sensitive Multithreaded Architecture
Austin, Texas September 17-September 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2000.8782862000 IEEE International Conference on ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
John S. Seng, University of California at San Diego
Dean M. Tullsen, University of California at San Diego
George Z.N. Cai, Intel Corporation
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures.
Citation:
John S. Seng, Dean M. Tullsen, George Z.N. Cai, "Power-Sensitive Multithreaded Architecture," iccd, pp.199, 2000 IEEE International Conference on Computer Design (ICCD'00), 2000
Usage of this product signifies your acceptance of the Terms of Use.