As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine a generalized design metric for simultaneously optimizing power and performance in nanometer-scale integrated circuits to achieve design-specific targets while incorporating electrothermal effects. This methodology is shown to provide a more meaningful basis to compare different design choices. The implications of technology scaling and parameter variations on this thermally-aware methodology are also presented.