Low-Power Design of 90-nm SuperH Processor Core

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http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.72

2005 International Conference on Comp ...

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	Tetsuya Yamaday, Masahide Abe, Yusuke Nitta, Kenji Oguray, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Tak ada, Fumio Arakawa, Osamu Nishii, T oshihiro Hattori, "Low-Power Design of 90-nm SuperH Processor Core," Computer Design, International Conference on, pp. 258-266, 2005 International Conference on Computer Design, 2005.

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	@article{ 10.1109/ICCD.2005.72, author = {Tetsuya Yamaday and Masahide Abe and Yusuke Nitta and Kenji Oguray and Manabu Kusaoke and Makoto Ishikawa and Motokazu Ozawa and Kiwamu Tak ada and Fumio Arakawa and Osamu Nishii and T oshihiro Hattori}, title = {Low-Power Design of 90-nm SuperH Processor Core}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2451-6}, pages = {258-266}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.72}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Low-Power Design of 90-nm SuperH Processor Core SN - 0-7695-2451-6 SP258 EP266 A1 - Tetsuya Yamaday, A1 - Masahide Abe, A1 - Yusuke Nitta, A1 - Kenji Oguray, A1 - Manabu Kusaoke, A1 - Makoto Ishikawa, A1 - Motokazu Ozawa, A1 - Kiwamu Tak ada, A1 - Fumio Arakawa, A1 - Osamu Nishii, A1 - T oshihiro Hattori, PY - 2005 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Tetsuya Yamaday, Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Masahide Abe, Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan

Yusuke Nitta, Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan

Kenji Oguray, Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Manabu Kusaoke, Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Makoto Ishikawa, Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Motokazu Ozawa, Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Kiwamu Tak ada, Hitachi ULSI systems CO., Ltd., 3-1-1, Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Fumio Arakawa, Hitachi, LTD, 1-280 Higashi-Koigajubo, kokubunji-shi, Tokyo, Japan

Osamu Nishii, Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan

T oshihiro Hattori, Renesas Technology Corp., 5-20-1, Josuihon-cho,Kodaira-shi, Tokyo Japan

A low power Super H embedded processor core, the SH-X2, has been desogned in 90-nm CMOS tehnology. The power consumption was reduced by using hierarchical fined grained clock gating to reduce the power consumption of the flip-flops and clock-tree synthesis and layout that support implementation of the clock gating, and several-level power evaluations for FTL refinement. With this clock gating and RTL refinement the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using Renesas low-power process with lowered voltage. Its performance efficiency was 25% better than that of a 130-nm-process SH-X.

Citation:

Tetsuya Yamaday, Masahide Abe, Yusuke Nitta, Kenji Oguray, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Tak ada, Fumio Arakawa, Osamu Nishii, T oshihiro Hattori, "Low-Power Design of 90-nm SuperH Processor Core," iccd, pp.258-266, 2005 International Conference on Computer Design, 2005

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