This paper presents the novel behavioral architecture of LSCIC (Layered Scalable Concurrent Image Compression) pre processor chip by utilizing scalable compression algorithm. This design separates enhanced and base layer pixels prior to concurrent compression operation in the coders. This paper also proposes a mathematical technique to snub the data signal errors by virtue of vector norm and Eigen values by controlling matrix condition number. Before attempting the behavioral design, a mathematical model is developed with timing and control signal constraints to avoid collision of signals. Simulation and synthesis procedures with successful synthesis report are also presented to verify the effectiveness of algorithm showing the correct operation of designed architecture.