PAC DSP Core and Application Processors
|
| Toronto, ON, Canada July 09-July 12 |
David Chang, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C. cwchang@itri.org.tw
I-tao Liao, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.
Jenq-kuen Lee, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.
Wen-feng Chen, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.
Shau-yin Tseng, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.
Chein-wei Jen, SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.
This paper provides an overview of the Parallel Architecture Core (PAC) project led by SoC Technology Center of Industrial Technology Research Institute (STC/ITRI) in Taiwan. The background of PAC project, a brief introduction to PAC core technologies, PAC SoC development suite, PAC benchmarks, and applications are presented. The main objective of the PAC development plan is to enhance industrial development competitiveness in the core technology related to key components, especially for portable multimedia applications.
Citation:
David Chang, I-tao Liao, Jenq-kuen Lee, Wen-feng Chen, Shau-yin Tseng, Chein-wei Jen, "PAC DSP Core and Application Processors," icme, pp.289-292, 2006 IEEE International Conference on Multimedia and Expo, 2006
Usage of this product signifies your acceptance of the
Terms of Use.
|
|
|
|
|
|
|
|