Complexity Analysis of H.264 Decoder for FPGA Design

Toronto, ON, Canada July 09-July 12

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http://doi.ieeecomputersociety.org/10.1109/ICME.2006.262765

2006 IEEE International Conference on ...

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	ASCII Text	x
	Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, Tiberiu Seceleanu, "Complexity Analysis of H.264 Decoder for FPGA Design," Multimedia and Expo, IEEE International Conference on, pp. 1253-1256, 2006 IEEE International Conference on Multimedia and Expo, 2006.

	BibTex	x
	@article{ 10.1109/ICME.2006.262765, author = {Tuomas Lindroth and Nastooh Avessta and Jukka Teuhola and Tiberiu Seceleanu}, title = {Complexity Analysis of H.264 Decoder for FPGA Design}, journal ={Multimedia and Expo, IEEE International Conference on}, volume = {0}, year = {2006}, isbn = {1-4244-0366-7}, pages = {1253-1256}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICME.2006.262765}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multimedia and Expo, IEEE International Conference on TI - Complexity Analysis of H.264 Decoder for FPGA Design SN - 1-4244-0366-7 SP1253 EP1256 A1 - Tuomas Lindroth, A1 - Nastooh Avessta, A1 - Jukka Teuhola, A1 - Tiberiu Seceleanu, PY - 2006 KW - null VL - 0 JA - Multimedia and Expo, IEEE International Conference on ER -

Tuomas Lindroth, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: tuomas.lindroth@utu.fi

Nastooh Avessta, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: nastooh.avessta@utu.fi@utu.fi

Jukka Teuhola, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: jukka.teuhola@utu.fi

Tiberiu Seceleanu, Dept. of Information Technology, Communication Systems Laboratory, University of Turku, Turku, Finland. E-mail: tiberiu.seceleanu@utu.fi

A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the H.264 decoder is presented. Since H.264 standard only specifies the syntax and semantics of the video stream and not the video codec itself, the selection process may be directed based upon the temporal complexity of different parts of the decoder. Here, we present the process flow of these parts using basic algebraic operators. The analysis of the required logic elements to implement the decoder, on various platforms, is presented.

Citation:

Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, Tiberiu Seceleanu, "Complexity Analysis of H.264 Decoder for FPGA Design," icme, pp.1253-1256, 2006 IEEE International Conference on Multimedia and Expo, 2006

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