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A Programmable Digital Neuro-Processor Design with Dynamically Reconfigurable Pipeline/Parallel Architecture
Taiwan December 14-December 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPADS.1998.7410141998 International Conference on Para ...
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Citation:
Y.-J. Jang, C.-H. Park, H.-S. Lee, "A Programmable Digital Neuro-Processor Design with Dynamically Reconfigurable Pipeline/Parallel Architecture," icpads, pp.18, 1998 International Conference on Parallel and Distributed Systems (ICPADS'98), 1998
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