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Scalable Core-Based Methodology and Synthesizable Core for Systematic Design
Columbus, Ohio August 14-August 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICPPW.2006.692006 International Conference on Para ...
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Ben A. Abderazek, The University of Electro-communications, Japan
Tsutomu Yoshinaga, The University of Electro-communications, Japan
Masahiro Sowa, The University of Electro-communications, Japan
The strong demand for complex and high performance embedded system-on-chip requires quick turn around design methodology and high performance cores. Thus, there is a clear need for new methodologies supporting efficient and fast design of these systems on complex platforms implementing both hardware and software modules. In this paper, we describe a novel scalable core-based methodology for systematic design environment of application specific heterogeneous multicore systems-on-chip (MCSoC). We also developed a high performance 32-bit Synthesizable QueueCore (QC-2) with single precision floating point support. The core is targeted for special purpose applications within our target MCSoC system. We present the architecture description and design results in a fair amount of details.
Citation:
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa, "Scalable Core-Based Methodology and Synthesizable Core for Systematic Design," icppw, pp.345-352, 2006 International Conference on Parallel Processing Workshops (ICPPW'06), 2006
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