Network-on-Chip (NoC) interconnections have been proposed to overcome the problems associated with long wires used in chip wide communications. They support asynchronous transfer of communication between cores within multicore systems-on-chips (MCSoCs). The design of such architectures is crucial for achieving high performance and energy efficient systems. However, the effectiveness of NoC based design depends on the adopted design methodology. Automatic design approach is highly desirable to increase system design productivity. This paper presents a new mathematical formulation for synthesizing application specific NoC architectures, such that the performance constraints are satisfied and the communication power consumption is minimized.