loading...
Implementation of design functions by available devices: a new algorithm
New Delhi, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.5120738th International Conference on VLSI ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
R.S. Mitra, P.S. Roop, A. Basu, "Implementation of design functions by available devices: a new algorithm," VLSI Design, International Conference on, pp. 30, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1995.512073,
author = {R.S. Mitra and P.S. Roop and A. Basu},
title = {Implementation of design functions by available devices: a new algorithm},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {30},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512073},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Implementation of design functions by available devices: a new algorithm
SN - 0-8186-6905-5
SP
EP
A1 - R.S. Mitra,
A1 - P.S. Roop,
A1 - A. Basu,
PY - 1995
KW - logic partitioning; logic CAD; circuit CAD; finite state machines; VLSI; design functions; available devices; CAD; function behaviors; mapping process; VLSI; finite state machines; logic partitioning
VL - 0
JA - VLSI Design, International Conference on
ER -
 
R.S. Mitra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.S. Roop, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Implementation of design functions by available devices is a key step in any design activity. This paper proposes an algorithm for automatically achieving a mapping between the functions and the devices. As an integral part of the approach, a novel scheme for modeling the device and the function behaviors is proposed, for reducing the complexity of the mapping process.
Index Terms:
logic partitioning; logic CAD; circuit CAD; finite state machines; VLSI; design functions; available devices; CAD; function behaviors; mapping process; VLSI; finite state machines; logic partitioning
Citation:
R.S. Mitra, P.S. Roop, A. Basu, "Implementation of design functions by available devices: a new algorithm," vlsid, pp.30, 8th International Conference on VLSI Design, 1995
Usage of this product signifies your acceptance of the Terms of Use.