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An asynchronous algorithm for sequential circuit test generation on a network of workstations
New Delhi, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.5120748th International Conference on VLSI ...
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J. Sienicki, M. Bushnell, P. Agrawal, V. Agrawal, "An asynchronous algorithm for sequential circuit test generation on a network of workstations," VLSI Design, International Conference on, pp. 36, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
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@article{ 10.1109/ICVD.1995.512074,
author = {J. Sienicki and M. Bushnell and P. Agrawal and V. Agrawal},
title = {An asynchronous algorithm for sequential circuit test generation on a network of workstations},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {36},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512074},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - An asynchronous algorithm for sequential circuit test generation on a network of workstations
SN - 0-8186-6905-5
SP
EP
A1 - J. Sienicki,
A1 - M. Bushnell,
A1 - P. Agrawal,
A1 - V. Agrawal,
PY - 1995
KW - logic testing; sequential circuits; parallel algorithms; automatic test software; fault diagnosis; asynchronous algorithm; sequential circuit test generation; workstation network; distributed algorithm; automatic test generation; fault list partitioning; multiple test generation processes; mathematical model
VL - 0
JA - VLSI Design, International Conference on
ER -
 
J. Sienicki, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
We present a distributed algorithm for automatic test generation for sequential circuits. Our system uses a network of workstations by partitioning the fault list. Multiple test generation processes are run on separate processors. Unlike a prior implementation, the communication of detected faults among processors is asynchronous, with all computers processing and broadcasting detected faults without synchronization. We thus accomplish a reduction in duplicated computation and a general improvement in the speedup as compared to the synchronized parallelization. Experimental results demonstrate superlinear speedups for some of the benchmark circuits. A mathematical model is presented to explain the speedups.
Index Terms:
logic testing; sequential circuits; parallel algorithms; automatic test software; fault diagnosis; asynchronous algorithm; sequential circuit test generation; workstation network; distributed algorithm; automatic test generation; fault list partitioning; multiple test generation processes; mathematical model
Citation:
J. Sienicki, M. Bushnell, P. Agrawal, V. Agrawal, "An asynchronous algorithm for sequential circuit test generation on a network of workstations," vlsid, pp.36, 8th International Conference on VLSI Design, 1995
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