PLA based synthesis and testing of hazard free logic

New Delhi, India January 04-January 07

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512089

8th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by U.K. Bhattacharyya Articles by I. Sen Gupta Articles by S. Shyama Nath Articles by P. Dutta

	ASCII Text	x
	U.K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta, "PLA based synthesis and testing of hazard free logic," VLSI Design, International Conference on, pp. 121, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512089, author = {U.K. Bhattacharyya and I. Sen Gupta and S. Shyama Nath and P. Dutta}, title = {PLA based synthesis and testing of hazard free logic}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {121}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512089}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - PLA based synthesis and testing of hazard free logic SN - 0-8186-6905-5 SP EP A1 - U.K. Bhattacharyya, A1 - I. Sen Gupta, A1 - S. Shyama Nath, A1 - P. Dutta, PY - 1995 KW - logic partitioning; logic CAD; design for testability; combinational circuits; logic testing; hazards and race conditions; programmable logic arrays; PLA based synthesis; hazard free logic; testing; combinational networks; multilevel network; supergate partitioning; multi-output circuits; testability VL - 0 JA - VLSI Design, International Conference on ER -

U.K. Bhattacharyya, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

I. Sen Gupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

S. Shyama Nath, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

P. Dutta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

This paper presents a divide and conquer approach for the hazard-free realization of combinational networks. The circuit is partitioned into a set of supergates which are individually made hazard-free. Since each supergate has to be implemented in two-level form, the circuit can be implemented as a multilevel network of PLAs. A modified supergate partitioning for multi-output circuits has also been proposed. Experiments to evaluate the testability of the synthesized circuits have been carried out.

Index Terms:

logic partitioning; logic CAD; design for testability; combinational circuits; logic testing; hazards and race conditions; programmable logic arrays; PLA based synthesis; hazard free logic; testing; combinational networks; multilevel network; supergate partitioning; multi-output circuits; testability

Citation:

U.K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta, "PLA based synthesis and testing of hazard free logic," vlsid, pp.121, 8th International Conference on VLSI Design, 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.