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Fully asynchronous, robust, high-throughput arithmetic structures
New Delhi, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.5120938th International Conference on VLSI ...
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P. Patra, D.S. Fussell, "Fully asynchronous, robust, high-throughput arithmetic structures," VLSI Design, International Conference on, pp. 141, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
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@article{ 10.1109/ICVD.1995.512093,
author = {P. Patra and D.S. Fussell},
title = {Fully asynchronous, robust, high-throughput arithmetic structures},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {141},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512093},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Fully asynchronous, robust, high-throughput arithmetic structures
SN - 0-8186-6905-5
SP
EP
A1 - P. Patra,
A1 - D.S. Fussell,
PY - 1995
KW - digital arithmetic; adders; multiplying circuits; asynchronous circuits; VLSI; integrated logic circuits; fully asynchronous structures; high-throughput arithmetic structures; bit serial adders; bit serial multipliers; delay-insensitive; RSA cryptosystems; scaleability
VL - 0
JA - VLSI Design, International Conference on
ER -
 
P. Patra, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.S. Fussell, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
This paper presents some novel circuit designs for bit serial adders and multipliers built out of some unusual, but well-defined circuit primitives. The circuits are fully delay-insensitive, provide good reliability and speed, and are easily verified. The structures are flexible and handle inputs of arbitrary lengths while being asymptotically optimal in speed and area. The scaleability of these circuits makes them. Very attractive for applications such as RSA cryptosystems which need very large operands and fast multiplication.
Index Terms:
digital arithmetic; adders; multiplying circuits; asynchronous circuits; VLSI; integrated logic circuits; fully asynchronous structures; high-throughput arithmetic structures; bit serial adders; bit serial multipliers; delay-insensitive; RSA cryptosystems; scaleability
Citation:
P. Patra, D.S. Fussell, "Fully asynchronous, robust, high-throughput arithmetic structures," vlsid, pp.141, 8th International Conference on VLSI Design, 1995
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