Futuristic portable real-time personal communication systems demand low power and high performance simultaneously. This poses a serious challenge to the designers since low power and high performance are two conflicting requirements. In this paper we propose a method called Wave Pipelined Architecture Folding (WPAF) which can be used effectively to reduce power while maintaining the operational throughput. WPAF exploits logic style and architecture along with the clock-free wave pipelining scheme to achieve low power. The technique comes with an additional advantage of reduced chip area which is important from the cost point of view.