A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology

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http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512105

8th International Conference on VLSI ...

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	ASCII Text	x
	V. Puvvada, S. Potla, T. Selvam, P.R. Suresh, "A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology," VLSI Design, International Conference on, pp. 192, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512105, author = {V. Puvvada and S. Potla and T. Selvam and P.R. Suresh}, title = {A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {192}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology SN - 0-8186-6905-5 SP EP A1 - V. Puvvada, A1 - S. Potla, A1 - T. Selvam, A1 - P.R. Suresh, PY - 1995 KW - CMOS integrated circuits; VLSI; integrated circuit technology; circuit analysis computing; transients; steady state simulation; n-guardring; p-guardring; latchup prevention; CMOS technology; remote transient; I/O buffer n-channel transistor; 2D device simulator; TMA-MEDICI; substrate resistance; 0.8 micron VL - 0 JA - VLSI Design, International Conference on ER -

V. Puvvada, Texas Instrum. (India) Pvt. Ltd., Bangalore, India

S. Potla, Texas Instrum. (India) Pvt. Ltd., Bangalore, India

T. Selvam, Texas Instrum. (India) Pvt. Ltd., Bangalore, India

P.R. Suresh, Texas Instrum. (India) Pvt. Ltd., Bangalore, India

The effect of using an n-guardring compared to p-guardring in preventing latchup due to remote transient at drain of I/O buffer n-channel transistor for 0.8 /spl mu/m CMOS technology is studied. Steady state simulations performed using a 2D device simulator TMA-MEDICI, show that the n-guardring is more effective compared to the p-guardring in increasing the remote trigger level for latchup. It is found that an increase in substrate resistance increased the remote trigger current level for latchup.

Index Terms:

CMOS integrated circuits; VLSI; integrated circuit technology; circuit analysis computing; transients; steady state simulation; n-guardring; p-guardring; latchup prevention; CMOS technology; remote transient; I/O buffer n-channel transistor; 2D device simulator; TMA-MEDICI; substrate resistance; 0.8 micron

Citation:

V. Puvvada, S. Potla, T. Selvam, P.R. Suresh, "A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology," vlsid, pp.192, 8th International Conference on VLSI Design, 1995

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