A general graph theoretic framework for multi-layer channel routing

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http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512109

8th International Conference on VLSI ...

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	ASCII Text	x
	R.K. Pal, A.K. Datta, S.P. Pal, M.M. Das, A. Pal, "A general graph theoretic framework for multi-layer channel routing," VLSI Design, International Conference on, pp. 202, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512109, author = {R.K. Pal and A.K. Datta and S.P. Pal and M.M. Das and A. Pal}, title = {A general graph theoretic framework for multi-layer channel routing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {202}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512109}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A general graph theoretic framework for multi-layer channel routing SN - 0-8186-6905-5 SP EP A1 - R.K. Pal, A1 - A.K. Datta, A1 - S.P. Pal, A1 - M.M. Das, A1 - A. Pal, PY - 1995 KW - network routing; VLSI; integrated circuit layout; circuit layout CAD; minimisation; graph theory; graph theoretic framework; multilayer channel routing; heuristics; track assignment; total wire length minimisation; two-layer VH routing model; VLSI layout; three-layer HVH routing model VL - 0 JA - VLSI Design, International Conference on ER -

R.K. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

A.K. Datta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

S.P. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

M.M. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

A. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near optimal number of tracks for several well-known benchmark channels in the two-layer VH. Three-layer HVH, and multi-layer V/sub i/H/sub i/ and V/sub i/H/sub i+1/ routing models. Within the same framework we also design an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models.

Index Terms:

network routing; VLSI; integrated circuit layout; circuit layout CAD; minimisation; graph theory; graph theoretic framework; multilayer channel routing; heuristics; track assignment; total wire length minimisation; two-layer VH routing model; VLSI layout; three-layer HVH routing model

Citation:

R.K. Pal, A.K. Datta, S.P. Pal, M.M. Das, A. Pal, "A general graph theoretic framework for multi-layer channel routing," vlsid, pp.202, 8th International Conference on VLSI Design, 1995

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