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A VLSI architecture for the computation of NURBS patches
New Delhi, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.5121338th International Conference on VLSI ...
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M.S. Gopi, S. Manohar, "A VLSI architecture for the computation of NURBS patches," VLSI Design, International Conference on, pp. 326, 8th International Conference on VLSI Design, 1995.
 
 
BibTex
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@article{ 10.1109/ICVD.1995.512133,
author = {M.S. Gopi and S. Manohar},
title = {A VLSI architecture for the computation of NURBS patches},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1995},
isbn = {0-8186-6905-5},
pages = {326},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512133},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A VLSI architecture for the computation of NURBS patches
SN - 0-8186-6905-5
SP
EP
A1 - M.S. Gopi,
A1 - S. Manohar,
PY - 1995
KW - parallel architectures; VLSI; splines (mathematics); computational geometry; VLSI architecture; NURBS patches; B-spline curves; computer graphics; geometric modeling; nonuniform rational B-spline; interactive modeling session; patch generation; complete hardware solution
VL - 0
JA - VLSI Design, International Conference on
ER -
 
M.S. Gopi, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
S. Manohar, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
B-Spline curves and patches are increasingly being used in several areas of computer graphics and geometric modeling. The rationalized counterpart of B-spline called Non-Uniform Rational B-Spline (NURBS) is invariably used in all the present day geometric modeling packages. For an interactive modeling session, thousands of NURBS patches have to be computed and drawn per second. Such performance is beyond the reach of even the most advanced workstations available today. Advances in hardware support for parametric curve and patch generation have thus acquired increased importance. The authors give a complete hardware solution for the generation of NURBS patches.
Index Terms:
parallel architectures; VLSI; splines (mathematics); computational geometry; VLSI architecture; NURBS patches; B-spline curves; computer graphics; geometric modeling; nonuniform rational B-spline; interactive modeling session; patch generation; complete hardware solution
Citation:
M.S. Gopi, S. Manohar, "A VLSI architecture for the computation of NURBS patches," vlsid, pp.326, 8th International Conference on VLSI Design, 1995
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