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VLSI floorplan generation and area optimization using AND-OR graph search
New Delhi, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.5121418th International Conference on VLSI ...
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P.S. Dasgupta, Comput. Center, Indian Inst. of Manage., Calcutta, India
S. Sur-Kolay, Comput. Center, Indian Inst. of Manage., Calcutta, India
B.B. Bhattacharya, Comput. Center, Indian Inst. of Manage., Calcutta, India
Floorplan design based on rectangular dualization is considered in two phases. First, given the adjacency graph and sets of aspect ratios of the blocks, a topology is generated which is likely to yield a minimum-area floorplan during the second phase of optimal sizing. Since the problem of finding such topology seems to be intractable, a heuristic search method using AND-OR graphs is employed in the top-down first phase. Novel heuristic estimates are used to reduce the search effort. For slicing topologies, a bottom-up polynomial-time algorithm is used to solve the second phase. Moreover, the first phase is able to report inherently nonslicible floorplans. The proposed method outperforms the existing techniques, as evident from the experimental results.
Index Terms:
VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; graph theory; VLSI floorplan generation; area optimization; AND-OR graph search; rectangular dualization; adjacency graph; aspect ratios; minimum-area floorplan; optimal sizing; heuristic search method; top-down first phase; search effort; bottom-up polynomial-time algorithm; nonslicible floorplans
Citation:
P.S. Dasgupta, S. Sur-Kolay, B.B. Bhattacharya, "VLSI floorplan generation and area optimization using AND-OR graph search," vlsid, pp.370, 8th International Conference on VLSI Design, 1995
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