Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers

New Delhi, India January 04-January 07

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512144

8th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by A. Guyot Articles by L. Montalvo Articles by A. Houelle Articles by H. Mehrez Articles by N. Vaucher

	ASCII Text	x
	A. Guyot, L. Montalvo, A. Houelle, H. Mehrez, N. Vaucher, "Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers," VLSI Design, International Conference on, pp. 386, 8th International Conference on VLSI Design, 1995.

	BibTex	x
	@article{ 10.1109/ICVD.1995.512144, author = {A. Guyot and L. Montalvo and A. Houelle and H. Mehrez and N. Vaucher}, title = {Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1995}, isbn = {0-8186-6905-5}, pages = {386}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512144}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers SN - 0-8186-6905-5 SP EP A1 - A. Guyot, A1 - L. Montalvo, A1 - A. Houelle, A1 - H. Mehrez, A1 - N. Vaucher, PY - 1995 KW - dividing circuits; redundant number systems; VLSI; CMOS logic circuits; integrated circuit layout; circuit layout CAD; logic CAD; layout synthesis; radix-2 dividers; pseudo-radix-4 dividers; digit-recurrence division; VLSI implementation; redundant number notation; carry-propagation-free addition/subtraction VL - 0 JA - VLSI Design, International Conference on ER -

A. Guyot, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France

L. Montalvo, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France

A. Houelle, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France

H. Mehrez, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France

N. Vaucher, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France

The digit-recurrence division relies on a sequence of addition/subtraction and shift operations in a manner similar to the paper-and-pencil approach, that gives a very regular structure suitable for efficient VLSI implementation. Speed is obtained through the use of redundant number notation allowing carry-propagation-free addition/subtraction with a delay independent of the size of the divisor. Since the quotient digits are obtained sequentially, the delay can theoretically be further reduced by recurring to higher-order radixes to obtain several quotient bits at once. This paper compares the synthesis of radix-2 and radix-4 dividers.

Index Terms:

dividing circuits; redundant number systems; VLSI; CMOS logic circuits; integrated circuit layout; circuit layout CAD; logic CAD; layout synthesis; radix-2 dividers; pseudo-radix-4 dividers; digit-recurrence division; VLSI implementation; redundant number notation; carry-propagation-free addition/subtraction

Citation:

A. Guyot, L. Montalvo, A. Houelle, H. Mehrez, N. Vaucher, "Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers," vlsid, pp.386, 8th International Conference on VLSI Design, 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.