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CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework
Bangalore, INDIA January 03-January 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.4894619th International Conference on VLSI ...
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R. W. Hartenstein, J. Becker, R. Kress, H. Reinig, "CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework," VLSI Design, International Conference on, pp. 81, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.
 
 
BibTex
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@article{ 10.1109/ICVD.1996.489461,
author = {R. W. Hartenstein and J. Becker and R. Kress and H. Reinig},
title = {CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1996},
issn = {1063-9667},
pages = {81},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489461},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework
SN - 1063-9667
SP
EP
A1 - R. W. Hartenstein,
A1 - J. Becker,
A1 - R. Kress,
A1 - H. Reinig,
PY - 1996
VL - 0
JA - VLSI Design, International Conference on
ER -
 
A novel hardware/software co-design framework (CoDe-X) is presented in this paper, where an Xputer iis used as universal accelerator based on a reconfigurable datapath hardware. CoDe-X accepts C-programs and car-ries out both, the profiling-driven host/accelerator partitioning for performance optimization, and (second lever!) the resource-driven sequential /structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable datapath resources.
Citation:
R. W. Hartenstein, J. Becker, R. Kress, H. Reinig, "CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework," vlsid, pp.81, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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