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Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation
Bangalore, INDIA January 03-January 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.4894649th International Conference on VLSI ...
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A. Boni and C. Morandi Abstract: Two novel BiCMOS latched comparators operating at 3.3V with 8bit resolution are presented. They achieve -2OOMHz operation and exhibit lower power consumption than the conventional architecture. The first resembles a conventional bipolar latched comparator, with a variable load resistance which changes its value three times during the acquisition cycle. It achieves the highest speed and the lowest power consumption. The second includes a differential amplifier which unbalances a ground-referenced latch by current mirror action. It may be adapted to even lower supply voltages and exhibits negligible kick-back effects. exhibits negligible kick-back effects.
Citation:
A. Boni, C. Morandi, "Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation," vlsid, pp.94, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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