P. Thadikaran, S. Chadravarty,
"Fast Algorithms for Computer IDDQ Tests for Combination Circuits,"
VLSI Design, International Conference on, pp. 103, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.
BibTex
x
@article{
10.1109/ICVD.1996.489466, author = {P. Thadikaran and S. Chadravarty}, title = {Fast Algorithms for Computer IDDQ Tests for Combination Circuits}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {103}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489466}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - VLSI Design, International Conference on TI - Fast Algorithms for Computer IDDQ Tests for Combination Circuits SN - 1063-9667 SP EP A1 - P. Thadikaran, A1 - S. Chadravarty, PY - 1996 VL - 0 JA - VLSI Design, International Conference on ER -
A system to generate IDDQ tests for bridging faults (BFs) and leakage faults in combinational CMOS circuit is de-scribed. Experimental results for different sets of BFs demonstrates the efficiency and flexibility of the approach.
Citation:
P. Thadikaran, S. Chadravarty, "Fast Algorithms for Computer IDDQ Tests for Combination Circuits," vlsid, pp.103, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb