Multilevel Factorization Technique for Pass Transistor Logic

Bangalore, INDIA January 03-January 06

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489630

9th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $0 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by A. Jaekel Articles by G.A. Jullien Articles by S. Bandyopadhyay

	ASCII Text	x
	A. Jaekel, G.A. Jullien, S. Bandyopadhyay, "Multilevel Factorization Technique for Pass Transistor Logic," VLSI Design, International Conference on, pp. 339, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996.

	BibTex	x
	@article{ 10.1109/ICVD.1996.489630, author = {A. Jaekel and G.A. Jullien and S. Bandyopadhyay}, title = {Multilevel Factorization Technique for Pass Transistor Logic}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {339}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489630}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Multilevel Factorization Technique for Pass Transistor Logic SN - 1063-9667 SP EP A1 - A. Jaekel, A1 - G.A. Jullien, A1 - S. Bandyopadhyay, PY - 1996 KW - pass transistor logic KW - algebraic factorization KW - PTL networks VL - 0 JA - VLSI Design, International Conference on ER -

A. Jaekel, VLSI Research Group, University of Windsor, Windsor, Ontario,

G.A. Jullien, VLSI Research Group, University of Windsor, Windsor, Ontario,

S. Bandyopadhyay, VLSI Research Group, University of Windsor, Windsor, Ontario,

Pass Transistor Logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks.

Index Terms:

pass transistor logic, algebraic factorization, PTL networks

Citation:

A. Jaekel, G.A. Jullien, S. Bandyopadhyay, "Multilevel Factorization Technique for Pass Transistor Logic," vlsid, pp.339, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.