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Geometric bipartitioning problem and its applications to VLSI
Bangalore, INDIA January 03-January 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.4896429th International Conference on VLSI ...
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P.S. Dasgupta, Comput. Center, Indian Inst. of Manage., Calcutta, India
A.K. Sen, Comput. Center, Indian Inst. of Manage., Calcutta, India
S.C. Nandy, Comput. Center, Indian Inst. of Manage., Calcutta, India
B.B. Bhattacharya, Comput. Center, Indian Inst. of Manage., Calcutta, India
We identify a new problem called geometric bipartitioning that is useful in VLSI layout design. Given a floorplan with rectilinear modules, the problem is to partition the floor by a staircase (monotone increasing) channel from one corner of the floor to its diagonally opposite corner, such that the numbers of modules in the two halves become equal. As the partition is heavily dependent on the geometry of the floorplan, this is quite different from the classical graph bisection problem. This problem can be captured using a weighted permutation graph with integer edge weights, which may be positive, negative or zero; the goal is to find a path between two designated nodes such that the absolute value of the sum of edge weights along the path is minimum. We then show that this problem is NP-complete, and present a heuristic algorithm based on branch-and-bound. Experimental results with benchmarks and randomly generated floorplans reveal that the algorithm produces optimal results quickly most of the time. Geometric bipartitioning problem may find many applications to hierarchical decomposition, floorplanning, and routing.
Index Terms:
circuit layout CAD; VLSI; network routing; graph theory; computational complexity; search problems; geometric bipartitioning problem; VLSI; layout design; floorplan; rectilinear modules; staircase; monotone increasing; geometry; classical graph bisection problem; weighted permutation graph; integer edge weights; designated nodes; absolute value; edge weights; NP-complete; heuristic algorithm; branch-and-bound; hierarchical decomposition; routing
Citation:
P.S. Dasgupta, A.K. Sen, S.C. Nandy, B.B. Bhattacharya, "Geometric bipartitioning problem and its applications to VLSI," vlsid, pp.400, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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