J. Shi, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
A. Randhar, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
D. Bhatia, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
This paper describes the floorplanning for FPGA based designs. In order to perform placement for very large designs, the currently followed approach of placing flat netlists is extremely time consuming. Also, managing large data sets, as in flat netlist files, is not trivial for performance driven designs. In this paper we describe an approach for the constraint-based FPGA floorplanning of flexible and fixed macro blocks. Our approach is to construct a floorplan of small area that respects the input constraint set. The input constraint set is derived from topological placement of the macro blocks based on both FPGA architectural constraints and ASIC design. Experimental results on FPGA floorplanning are also presented for large benchmark examples.
Index Terms:
integrated circuit layout, macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, ASIC design, large benchmark examples, VLSI floorplanning, heuristic algorithm
Citation:
J. Shi, A. Randhar, D. Bhatia, "Macro Block Based FPGA Floorplanning," vlsid, pp.21, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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