A Technology Mapper for Xilinx FPGAs

Hyderabad, India January 04-January 07

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.567961

Tenth International Conference on VLS ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Madhav Y. Chikodikar Articles by Shridhar Laddha Articles by Ashish Sirasao

	ASCII Text	x
	Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao, "A Technology Mapper for Xilinx FPGAs," VLSI Design, International Conference on, pp. 57, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.567961, author = {Madhav Y. Chikodikar and Shridhar Laddha and Ashish Sirasao}, title = {A Technology Mapper for Xilinx FPGAs}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {57}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.567961}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Technology Mapper for Xilinx FPGAs SN - 1063-9667 SP EP A1 - Madhav Y. Chikodikar, A1 - Shridhar Laddha, A1 - Ashish Sirasao, PY - 1997 VL - 0 JA - VLSI Design, International Conference on ER -

Madhav Y. Chikodikar, Silicon Automation Systems

Shridhar Laddha, Silicon Automation Systems

Ashish Sirasao, Silicon Automation Systems

This paper presents a method for area optimal technology mapping for Xilinx FPGAs. The method is modification of the method described and covers uniformly XC2000, XC3000 and XC4000 series of Xilinx FPGAs. The method addresses mapping of combinational and sequential logic onto Xilinx FPGAs. The results compare favorably with the existing mappers and the CLB estimates provided by the mapper are comparable with the CLB count obtained after passing the circuit through Xilinx implementation kit.

Citation:

Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao, "A Technology Mapper for Xilinx FPGAs," vlsid, pp.57, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.