S. M. Kang, Adv. Design Technol., Motorola Inc., Austin, TX, USA
This paper presents a technique for transistor-level timing simulation of MOS circuits driving RC interconnect loads. The RC interconnect is represented as a reduced-order model (e.g. /spl pi/-model). An effective capacitance is analytically derived from the reduced-order model by local linearization of the MOS devices in the driver circuit and is dynamically updated as the output voltage and regions of operation of the MOS devices in the driver circuit change. The effective capacitance is then applied as a load to the driver circuit and the output waveform is obtained by analytically solving the nonlinear state equation of the driving node. Extensive simulation results under various loading conditions and input transition times are provided to demonstrate the accuracy and efficiency of this technique.
Index Terms:
MOS integrated circuits, MOS circuits driving RC interconnects, fast timing simulation, transistor-level timing simulation, RC interconnect loads, reduced-order model, /spl pi/-model, effective capacitance, local linearization, driver circuit, dynamic updating, output waveform analysis, nonlinear state equation, loading conditions, input transition times, ILLIADS2
Citation:
A. Dharchoudhuri, S. M. Kang, "Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects," vlsid, pp.111, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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