loading...
Formal Techniques for Hardware Allocation
Hyderabad, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568070Tenth International Conference on VLS ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
J.M. Mendias, R. Hermida, M. Fernández, "Formal Techniques for Hardware Allocation," VLSI Design, International Conference on, pp. 161, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1997.568070,
author = {J.M. Mendias and R. Hermida and M. Fernández},
title = {Formal Techniques for Hardware Allocation},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1997},
issn = {1063-9667},
pages = {161},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568070},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Formal Techniques for Hardware Allocation
SN - 1063-9667
SP
EP
A1 - J.M. Mendias,
A1 - R. Hermida,
A1 - M. Fernández,
PY - 1997
KW - high level synthesis
KW - hardware allocation
KW - hardware reusability
KW - behavioral synthesis
KW - semantics
KW - hardware modules
KW - symbolic manipulation
KW - synthesis tool
KW - candidate operators identification
VL - 0
JA - VLSI Design, International Conference on
ER -
 
J.M. Mendias, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
R. Hermida, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
M. Fernández, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
Hardware reusability is a key aspect of behavioral synthesis which is mainly based on the possibility of implementing several operators with a single module. This shared use of resources is heavily dependent on the ability of the synthesis tool to identify candidate operators to be merged. Some ideas for the creation of a uniform framework where the semantics of hardware modules can be formally expressed are presented in this paper. The application to hardware allocation through symbolic manipulation is also addressed.
Index Terms:
high level synthesis, hardware allocation, hardware reusability, behavioral synthesis, semantics, hardware modules, symbolic manipulation, synthesis tool, candidate operators identification
Citation:
J.M. Mendias, R. Hermida, M. Fernández, "Formal Techniques for Hardware Allocation," vlsid, pp.161, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
Usage of this product signifies your acceptance of the Terms of Use.