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New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults
Hyderabad, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568094Tenth International Conference on VLS ...
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Debesh K. Das, Jadavpur University
Susanta Chakraborty, Kalyani University
Bhargab B. Bhattacharya, Indian Statistical Institute
This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5.2^n vectors to the modified CUT, and counting the number of 1's in the output response. The second method uses the same TPG, but faults are detected by self comparison of the output stream. Finally, we propose a new kind of adaptive BIST technique, where the test pattern generator (TPG) is driven by the past outputs of the CUT itself. The latter two methods detect multiple stuck-open faults as well. In all the three cases, the TPG is universal, i.e., it does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector is to be determined, nor any fault dictionary is required. Thus these approaches provide simplicity, less testing time and test data, and compare favorably with the earlier BIST designs for CMOS circuits.
Index Terms:
BIST, CMOS complex cells, stuck-open faults
Citation:
Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya, "New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults," vlsid, pp.303, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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