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Asynchronous Implementation of Synchronous Esterel Specifications
Hyderabad, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568106Tenth International Conference on VLS ...
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Raj S Mitra, Cadence Design Systems Pvt Ltd
Bishnupriya Bhattacharya, Cadence Design Systems Pvt Ltd
Luciano Lavagno, Cadence Berkeley Labs
The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However, for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm, so that the user is aware of the executable semantics that he should expect.
Index Terms:
Embedded Systems, Executable Specifications, Hardware Software Codesign
Citation:
Raj S Mitra, Bishnupriya Bhattacharya, Luciano Lavagno, "Asynchronous Implementation of Synchronous Esterel Specifications," vlsid, pp.348, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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