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A Simulation Methodology for Software Energy Evaluation
Hyderabad, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568187Tenth International Conference on VLS ...
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H. Mehta, R.M. Owens, M.J. Irwin, "A Simulation Methodology for Software Energy Evaluation," VLSI Design, International Conference on, pp. 509, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.
 
 
BibTex
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@article{ 10.1109/ICVD.1997.568187,
author = {H. Mehta and R.M. Owens and M.J. Irwin},
title = {A Simulation Methodology for Software Energy Evaluation},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1997},
issn = {1063-9667},
pages = {509},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568187},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Simulation Methodology for Software Energy Evaluation
SN - 1063-9667
SP
EP
A1 - H. Mehta,
A1 - R.M. Owens,
A1 - M.J. Irwin,
PY - 1997
KW - pipeline processing
KW - simulation
KW - software energy
KW - pipelined DLX processor
KW - software pipelining
KW - micro-instruction
KW - compilation optimization
KW - recursion elimination
KW - algorithm
KW - loop unrolling
KW - architecture
VL - 0
JA - VLSI Design, International Conference on
ER -
 
H. Mehta, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
We describe a comprehensive simulation methodology and tool for evaluation of software energy for the pipelined DLX processor. Energy models for each module of DLX are built and the energy is evaluated during run time execution. The input to the simulator are the instructions of the program and the simulator estimates energy of each micro-instruction using the energy models. Our simulator allows exploration of energy by allowing architecture modification, experimentation with different software techniques (compilation optimizations, algorithm evaluation) and also allows simultaneous interplay of both hardware and software techniques. The usefulness of this simulator is demonstrated by evaluating certain compilation optimizations (loop unrolling, software pipelining, recursion elimination etc.) and algorithms.
Index Terms:
pipeline processing, simulation, software energy, pipelined DLX processor, software pipelining, micro-instruction, compilation optimization, recursion elimination, algorithm, loop unrolling, architecture
Citation:
H. Mehta, R.M. Owens, M.J. Irwin, "A Simulation Methodology for Software Energy Evaluation," vlsid, pp.509, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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