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On Test Compaction Objectives for Combinational and Sequential Circuits
India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646618Eleventh International Conference on ...
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Irith Pomeranz, Sudhakar M. Reddy, "On Test Compaction Objectives for Combinational and Sequential Circuits," VLSI Design, International Conference on, pp. 279, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.1998.646618,
author = {Irith Pomeranz and Sudhakar M. Reddy},
title = {On Test Compaction Objectives for Combinational and Sequential Circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {1998},
issn = {1063-9667},
pages = {279},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646618},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - On Test Compaction Objectives for Combinational and Sequential Circuits
SN - 1063-9667
SP
EP
A1 - Irith Pomeranz,
A1 - Sudhakar M. Reddy,
PY - 1998
KW - combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Irith Pomeranz, University of Iowa
Sudhakar M. Reddy, University of Iowa
We study storage schemes for test patterns and test responses of combinational and synchronous sequential circuits which are tested off-line by a tester. These storage schemes provide new objectives for test compaction beyond the need to reduce the test set size as much as possible. We report on several postprocessing methods to reduce the storage requirements of a given test set and present experimental evidence pointing to the possibility of reducing the storage requirements by using appropriate compaction objectives during test generation.
Index Terms:
combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On Test Compaction Objectives for Combinational and Sequential Circuits," vlsid, pp.279, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998
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