Fast Arithmetic on Xilinx 5200 FPGA

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http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646626

Eleventh International Conference on ...

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	ASCII Text	x
	B. Laurent, G. Bosco, G. Saucier, "Fast Arithmetic on Xilinx 5200 FPGA," VLSI Design, International Conference on, pp. 322, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646626, author = {B. Laurent and G. Bosco and G. Saucier}, title = {Fast Arithmetic on Xilinx 5200 FPGA}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {322}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646626}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Fast Arithmetic on Xilinx 5200 FPGA SN - 1063-9667 SP EP A1 - B. Laurent, A1 - G. Bosco, A1 - G. Saucier, PY - 1998 KW - (do not appear on the paper): Arithmetic KW - Xilinx 5200 FPGA KW - Performance KW - Place and route VL - 0 JA - VLSI Design, International Conference on ER -

B. Laurent, Institut National Polytechnique de Grenoble / CSI

G. Bosco, Institut National Polytechnique de Grenoble / CSI

G. Saucier, Institut National Polytechnique de Grenoble / CSI

In this paper, classical adder and multiplier architectures applied to Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools.

Index Terms:

(do not appear on the paper): Arithmetic, Xilinx 5200 FPGA, Performance, Place and route

Citation:

B. Laurent, G. Bosco, G. Saucier, "Fast Arithmetic on Xilinx 5200 FPGA," vlsid, pp.322, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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