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IDDQ-Testability of Tree Circuits
Goa, India January 10-January 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.74512812th International Conference on VLSI ...
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The quality of CMOS circuits can be increased by performing IDDQ testing. For regular circuits constructed from identical modules, defects localized to a single module detectable by current testing can be sensitized by exhaustively applying all input patterns to each circuit module. Regular circuits for which every module in arbitrarily large circuit can have all input patterns applied are defined to be IDDQ-testable. The IDDQ-testing properties of a class of regular circuits called tress are investigated. We present the conditions for one-dimensional and tree array circuits to be IDDQ-testable. We also present conditions for these circuits to be CIDDQ-testable, that is, IDDQ-testable with a constant number of tests independent of the circuit's size. Practical circuits such as comparators and carry-lookahead adders are used to illustrate the derived conditions.
Citation:
R.D. (Shawn) Blanton, "IDDQ-Testability of Tree Circuits," vlsid, pp.78, 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', 1999
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