In recent years, fractal encoding of image (using Iterated Function Systems) has emerged as a potent technique in the field of image compression. This method has comparable or sometimes better performance as compared to most others, specially, with respect to quality of reconstructed image and compression ratio. But most fractal encoding methods are very slow that prevent them from realtime processing of images. Since fractal encoding methods have ample data parallelism and spatial/temporal recurrence, there is lot of scope for designing efficient VLSI architectures for them. In this paper, we have selected a suitable encoding scheme and designed the VLSI architecture for it. The proposed architecture has been simulated and synthesized, using Verilog and Synergy of Cadence Design Tools. The architecture employs principles of pipelining and parellelism to enhance performance with respect to speed of compression. Simulation and synthesis results show good time performance for the proposed chip.