Processor Evaluation in an Embedded Systems Design Environment

Calcutta, India January 04-January 07

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812591

13th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by T. Vinod Kumar Gupta Articles by Purvesh Sharma Articles by M Balakrishnan Articles by Sharad Malik

	ASCII Text	x
	T. Vinod Kumar Gupta, Purvesh Sharma, M Balakrishnan, Sharad Malik, "Processor Evaluation in an Embedded Systems Design Environment," VLSI Design, International Conference on, pp. 98, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812591, author = {T. Vinod Kumar Gupta and Purvesh Sharma and M Balakrishnan and Sharad Malik}, title = {Processor Evaluation in an Embedded Systems Design Environment}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {98}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812591}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Processor Evaluation in an Embedded Systems Design Environment SN - 1063-9667 SP EP A1 - T. Vinod Kumar Gupta, A1 - Purvesh Sharma, A1 - M Balakrishnan, A1 - Sharad Malik, PY - 2000 KW - Processor architecture KW - ASIP KW - Application profiling KW - Real-time constraints KW - ASAP scheduler KW - Architecture constrained scheduler VL - 0 JA - VLSI Design, International Conference on ER -

T. Vinod Kumar Gupta, Indian Institute of Technology

Purvesh Sharma, Indian Institute of Technology

M Balakrishnan, Indian Institute of Technology

Sharad Malik, Princeton University

In this paper, we present a novel methodology for processor evaluation in an embedded systems design environment. This evaluation can help in either selecting a suitable processor core or in evaluating changes to an ASIP. The processor evaluation is carried out in two stages. First, an architecture independent stage in which processors are rejected based on key application parameters and secondly, an architecture dependent stage in which performance is estimated on selected processors. The contribution of our work includes identification of application parameters which can influence processor selection, a mechanism to capture widely varying processor architectures and an instruction constrained scheduler. Initial experimental results suggest the potential of this approach.

Index Terms:

Processor architecture, ASIP, Application profiling, Real-time constraints, ASAP scheduler, Architecture constrained scheduler

Citation:

T. Vinod Kumar Gupta, Purvesh Sharma, M Balakrishnan, Sharad Malik, "Processor Evaluation in an Embedded Systems Design Environment," vlsid, pp.98, 13th International Conference on VLSI Design, 2000

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.