Scalable Pipelined Micro-Architecture for Wavelet Transform

Calcutta, India January 04-January 07

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http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812599

13th International Conference on VLSI ...

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	ASCII Text	x
	Kolin Paul, P. Pal Chaudhuri, D. Roy Chowdhury, "Scalable Pipelined Micro-Architecture for Wavelet Transform," VLSI Design, International Conference on, pp. 144, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812599, author = {Kolin Paul and P. Pal Chaudhuri and D. Roy Chowdhury}, title = {Scalable Pipelined Micro-Architecture for Wavelet Transform}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {144}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812599}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Scalable Pipelined Micro-Architecture for Wavelet Transform SN - 1063-9667 SP EP A1 - Kolin Paul, A1 - P. Pal Chaudhuri, A1 - D. Roy Chowdhury, PY - 2000 VL - 0 JA - VLSI Design, International Conference on ER -

Kolin Paul, Bengal Engineering College (Deemed University)

P. Pal Chaudhuri, Bengal Engineering College (Deemed University)

D. Roy Chowdhury, Indian Institute of Technology

A new scalable pipelined micro-architecture has been proposed for evaluating the Discrete Wavelet Transform which demands very high processing power. The proposed scheme does away with the explicit multiply operation which is both expensive as well time consuming and provides an innovative method to obtain the transformed values of the discrete samples at every clock cycle.

Citation:

Kolin Paul, P. Pal Chaudhuri, D. Roy Chowdhury, "Scalable Pipelined Micro-Architecture for Wavelet Transform," vlsid, pp.144, 13th International Conference on VLSI Design, 2000

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